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HD74ALVCH16832
1-to-4 Address Register / Driver with 3-state Outputs
REJ03D0030-0400Z (Previous ADE-205-214B(Z)) Rev.4.00 Oct.02.2003
Description
This 1-bit to 4-bit address register / driver is designed for 2.3 V to 3.6 V VCC operation. The device is ideal for use in applications in which a single address bus is driving four separate memory locations. The HD74ALVCH16832 can be used as a buffer or a register, depending on the logic level of the select (SEL) input. When SEL is a logic high, the device is in the buffer mode. The outputs follow the inputs and are controlled by the two output enable (OE) inputs. Each OE controls two groups of seven outputs. ) When SEL is a logic low, the device is in the register mode. The register is an edge triggered D-type flip flop. On the positive transition of the clock (CLK) input, data at the A inputs is stored in the internal registers. OE controls operate the same as in the buffer mode. When OE is a logic low, the outputs are in a normal logic state (high or low logic level). When OE is a logic high, the outputs are in the high impedance state. Neither SEL nor OE affect the internal operation of the flip flops. Old data can be retained or new data can be entered while the outputs are in the high impedance state. To ensure the high impedance state during power up or power down, OE should be tied to VCC through a pull up resistor; the minimum value of the resistor is determined by the current sinking capability of the driver. Active bus hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
Features
* * * * * VCC = 2.3 V to 3.6 V Typical VOL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25C) Typical VOH undershoot > 2.0 V (@VCC = 3.3 V, Ta = 25C) High output current 24 mA (@VCC = 3.0 V) Bus hold on data inputs eliminates the need for external pull up / pull down resistors
Rev.4.00, Oct.02.2003, page 1 of 11
HD74ALVCH16832
Function Table
Inputs OE H L L L L SEL X H H L L CLK X X X A X L H L H Z L H L H Output Y
H : High level L : Low level X : Immaterial Z : High impedance : Low to high transition
Rev.4.00, Oct.02.2003, page 2 of 11
HD74ALVCH16832
Pin Arrangement
4Y1 1 3Y1 2 GND 3 2Y1 4 1Y1 5 VCC 6 A1 7 GND 8 A2 9 GND 10 A3 11 VCC 12 NC 13 GND 14 CLK 15 OE1 16 OE2 17 SEL 18 GND 19 A4 20 A5 21 VCC 22 GND 23 A6 24 GND 25 A7 26 VCC 27 4Y7 28 3Y7 29 GND 30 2Y7 31 1Y7 32
64 1Y2 63 2Y2 62 GND 61 3Y2 60 4Y2 59 VCC 58 1Y3 57 2Y3 56 GND 55 3Y3 54 4Y3 53 GND 52 VCC 51 GND 50 1Y4 49 2Y4 48 3Y4 47 4Y4 46 GND 45 1Y5 44 2Y5 43 VCC 42 3Y5 41 4Y5 40 GND 39 GND 38 VCC 37 1Y6 36 2Y6 35 GND 34 3Y6 33 4Y6
(Top view)
Rev.4.00, Oct.02.2003, page 3 of 11
HD74ALVCH16832
Absolute Maximum Ratings
Item Supply voltage Input voltage *1 Output voltage
*1, 2
Symbol VCC VI VO IIK IOK IO ICC or IGND PT Tstg
Ratings -0.5 to 4.6 -0.5 to 4.6 -0.5 to VCC +0.5 -50 50 50 100 1 -65 to 150
Unit V V V mA mA mA mA W C
Conditions
Input clamp current Output clamp current Continuous output current VCC, GND current / pin Maximum power dissipation *3 at Ta = 55C (in still air) Storage temperature Notes:
VI < 0 VO < 0 or VO > VCC VO = 0 to VCC TSSOP
Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rated conditions for extended periods may affect device reliability. 1. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed. 2. This value is limited to 4.6 V maximum. 3. The maximum package power dissipation is calculated using a junction temperature of 150C and a board trace length of 750 mils.
Recommended Operating Conditions
Item Supply voltage Input voltage Output voltage High level output current Symbol VCC VI VO IOH Min 2.3 0 0 -- -- -- Low level output current IOL -- -- -- Input transition rise or fall rate Operating temperature t / v Ta 0 -40 Max 3.6 VCC VCC -12 -12 -24 12 12 24 10 85 ns / V C mA Unit V V V mA VCC = 2.3 V VCC = 2.7 V VCC = 3.0 V VCC = 2.3 V VCC = 2.7 V VCC = 3.0 V Conditions
Note: Unused control inputs must be held high or low to prevent them from floating.
Rev.4.00, Oct.02.2003, page 4 of 11
HD74ALVCH16832
Logic Diagram
OE1 OE2 CLK A1
16 5 17 15 7 4
1Y1 2Y1 3Y1 4Y1
CLK
2
D
Q
1
SEL
18
To six other channels hannels
Rev.4.00, Oct.02.2003, page 5 of 11
HD74ALVCH16832
Electrical Characteristics
(Ta = -40 to 85C)
Item Input voltage Symbol VCC (V) *1 VIH VIL Output voltage VOH 2.3 to 2.7 2.7 to 3.6 2.3 to 2.7 2.7 to 3.6 2.3 to 3.6 2.3 2.3 2.7 3.0 3.0 VOL 2.3 to 3.6 2.3 2.3 2.7 3.0 Input current IIN IIN (hold) 3.6 2.3 2.3 3.0 3.0 3.6 Off state output current IOZ ICC 3.6 3.6 3.0 to 3.6 Quiescent supply current ICC Min 1.7 2.0 -- -- VCC-0.2 2.0 1.7 2.2 2.4 2.0 -- -- -- -- -- -- 45 -45 75 -75 -- -- -- -- Max -- -- 0.7 0.8 -- -- -- -- -- -- 0.2 0.4 0.7 0.4 0.55 5 -- -- -- -- 500 10 40 750 A A A A V IOH = -100 A IOH = -6 mA, VIH = 1.7 V IOH = -12 mA, VIH = 1.7 V IOH = -12 mA, VIH = 2.0 V IOH = -12 mA, VIH = 2.0 V IOH = -24 mA, VIH = 2.0 V IOL = 100 A IOL = 6 mA, VIL = 0.7 V IOL = 12 mA, VIL = 0.7 V IOL = 12 mA, VIL = 0.8 V IOL = 24 mA, VIL = 0.8 V VIN = VCC or GND VIN = 0.7 V VIN = 1.7 V VIN = 0.8 V VIN = 2.0 V VIN = 0 to 3.6 V *2 VOUT = VCC or GND VIN = VCC or GND VIN = one input at (VCC-0.6) V, other inputs at VCC or GND Unit V Test Conditions
Notes: 1. For conditions shown as Min or Max, use the appropriate values under recommended operating conditions. 2. This is the bus hold maximum dynamic current required to switch the input from one state to another.
Rev.4.00, Oct.02.2003, page 6 of 11
HD74ALVCH16832
Switching Characteristics
(Ta = -40 to 85C)
Item Maximum clock frequency Symbol VCC (V) fmax 2.50.2 2.7 3.30.3 Propagation delay time tPLH tPHL 2.50.2 2.7 3.30.3 2.50.2 2.7 3.30.3 2.50.2 2.7 3.30.3 Output enable time tZH tZL Output disable time tHZ tLZ Setup time tsu 2.50.2 2.7 3.30.3 2.50.2 2.7 3.30.3 2.50.2 2.7 3.30.3 Hold time th 2.50.2 2.7 3.30.3 Pulse width tw 2.50.2 2.7 3.30.3 Input capacitance Output capacitance CIN CO 3.3 3.3 3.3 Min 150 150 150 1.2 -- 1.6 1.1 -- 1.5 1.3 -- 1.7 1.1 -- 1.2 1.4 -- 1.6 2.0 2.0 1.6 0.7 0.5 1.1 3.3 3.3 3.3 -- -- -- Typ -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- 4.5 5.0 7.5 Max -- -- -- 4.0 4.1 3.6 4.5 4.4 3.9 5.2 5.2 4.4 5.1 5.0 4.3 5.5 4.7 4.5 -- -- -- -- -- -- -- -- -- -- -- -- pF pF Control inputs Data inputs Outputs ns ns ns ns OE Y ns OE Y SEL Y CLK Y ns A Y Unit MHz FROM (Input) TO (Output)
Rev.4.00, Oct.02.2003, page 7 of 11
HD74ALVCH16832
Test Circuit
See under table 500 S1 OPEN
*1
GND 500
CL
Load Circuit for Outputs Symbol t PLH / t PHL t su / t h / t w t ZH/ t HZ t ZL / t LZ CL
Vcc=2.50.2V Vcc=2.7V, 3.30.3V
OPEN GND 2 x VCC 30 pF
OPEN GND 6.0 V 50 pF
Note:
1.
CL includes probe and jig capacitance.
Rev.4.00, Oct.02.2003, page 8 of 11
HD74ALVCH16832 Waveforms - 1
tr 90 % Input 10 % t PLH Vref 90 % Vref 10 % t PHL tf VIH GND
VOH Output Vref Vref VOL
Waveforms - 2
tr 90 % Timing Input 10 % tsu Vref th GND VIH Data Input Vref Vref GND tw VIH Input Vref Vref GND VIH
Rev.4.00, Oct.02.2003, page 9 of 11
HD74ALVCH16832 Waveforms - 3
tf Output Control 90 % Vref 10 % t ZL Vref t ZH Waveform - B Vref t HZ Vref2 10 % t LZ tr 90 % Vref GND VOH1 Waveform - A Vref1 VOL VOH VOL1 TEST VIH Vref Vref1 Vref2 VOH1 VOL1
Vcc=2.50.2 V Vcc = 2.7 V, 3.30.3 V
VIH
VCC
2.7 V
1/2 VCC 1.5 V VOL +0.15 V VOL +0.3 V VOH-0.15 V VOH-0.3 V VCC GND 3.0 V GND
Notes:
1.
2. 3. 4.
All input pulses are supplied by generators having the following characteristics : PRR 10 MHz, Zo = 50 , tr 2.0 ns, tf 2.0 ns. (VCC = 2.50.2 V) PRR 10 MHz, Zo = 50 , tr 2.5 ns, tf 2.5 ns. (VCC = 2.7 V, 3.30.3 V) Waveform - A is for an output with internal conditions such that the output is low except when disabled by the output control. Waveform - B is for an output with internal conditions such that the output is high except co when disabled by the output control. The output are measured one at a time with one transition per measurement.
Rev.4.00, Oct.02.2003, page 10 of 11
HD74ALVCH16832
Package Dimensions
As of January, 2003
Unit: mm
33
17.0 17.2 Max 64
1 0.50 *0.20 0.05 0.08 M 0.90 Max
32
6.10
1.0 8.10 0.20 0 - 8 0.5 0.1
*0.15 0.05
0.08
0.10 0.05
1.20 Max
*Ni/Pd/Au plating
Package Code JEDEC JEITA Mass (reference value)
TTP-64DV -- Conforms 0.26 g
Rev.4.00, Oct.02.2003, page 11 of 11
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